The present invention relates to a floating-point number arithmetic circuit, and more particularly to a floating-point number arithmetic circuit for handling immediate values and a processor for executing floating-point number instructions with immediate values.
If data which an arithmetic circuit is to operate on is stored in a memory, then when the data is to be supplied to the arithmetic unit, the data needs to be read from the memory. Some processors handle data that is stored in a memory as data to operate on by providing a field (a memory operand) which specifies an address of the memory where the data to operate on is stored, as an operand of an arithmetic instruction.
However, if a memory operand is provided in an arithmetic instruction, then it is necessary to access the specified memory address after the arithmetic instruction is interpreted. As a result, it takes a long time until all the data becomes available.
According to a load-store architecture exemplified by RISCs (Reduced Instruction Set Computers) in recent years, a loading instruction for reading data from a memory into a register and an arithmetic instruction for operating on the data are separate from each other to eliminate latency in an instruction thereby facilitating instruction scheduling for faster operations according to a compiler. The same architecture is also employed with respect to instruction sets for arithmetic processors that are combined with processors (see, for example, Nonpatent document 1: “IA-32 Intel(R) Architecture Software Developer's Manual Volume 1: Basic Architecture”, Intel Corporation, 2004).